The prior art is replete with various package configurations for semiconductor chips. In recent years, the cost of such packages has, in many cases, outdistanced the cost of the chips. To overcome this cost problem, a technique known as Tape Automated Bonding (TAB) packaging has come into being and it is especially useful with lower cost, low power dissipation integrated circuits. TAB packaging involves the use of a web of material, generally called a carrier tape, to carry electrically conductive leads which provide connections between the chip and the outside world. The carrier tape is incremented past a number of operating stations, one of which places a chip on an inner cluster of the conductive leads, which inner cluster is then bonded to connecting pads on the chip. The tape is then incremented to a station where the active face of the chip, including the inner lead bonds may be coated with a passivating material. The tape is then moved to a further station where the outer cluster of leads on the carrier tape is severed from the tape. The tape/chip combination is then registered with conductive pads residing on an underlying circuit board and the outer leads are bonded to the conductive pads. The circuit board-chip combination is then available for further processing.
TAB packaging is, by its nature, inexpensive. Its use has been mainly restricted to low power dissipation circuits as it is quite difficult to apply heat sinks to a TAB package structure. The main (and often only) physical interconnection between a chip and an underlying circuit board in a TAB package is via bonds between the tape-carried outer leads and the underlying conductive pads on the circuit board. To attach a cast or extruded heat sink to the chip in a TAB package is impractical as, in the event of mechanical vibration or strain, the chip will tend to pull away from the circuit board and the exerted forces may exceed the rupture strength of the lead bonds or the tape itself.
The prior art has attempted to solve the heat dissipation problems inherent with TAB packages via a number of routes. U.S. Pat. No. 4,459,607 to Reid attempts to solve the problem by emplacing the chip "back down" on a metal base plate causing the chip to be configured in a face-up orientation. One problem with this arrangement is that it calls for the use of a double metal clad plastic carrier rather than a less expensive single metal clad carrier. Furthermore, Reid suggests that the chip with its metal backing be emplaced so that the metal backing is flush with the underlying circuit board to enable the board to provide a more extensive heat sink capability. This configuration results in a relatively long thermal path before convective cooling is encountered. In other words, if the semiconductor ]unctions within the chip overheat, that heat must first be transferred from the chip to the underlying metal base and thence into a thermally conductive substrate where, finally, it is available to be dissipated via convective or forced air flow. Ideally, the metal heat dissipator should, itself, be subjected to convective air flow for cooling purposes.
In U.S. Pat. No. 4,396,936 to McIver et al, a chip is mounted face down on a substrate in which there is formed a plurality of thermal passages. A thermally conductive material fills the passages and provides heat dissipating pathways for chip-developed heat. This technique suffers from the same problem which besets Reid, (i.e., a long thermal pathway).
While much of the heat sink prior art shows the use of extruded aluminum or copper heat sinks of some substantial mass, other prior art shows the use of relatively thin sheets of copper or aluminum for heat sink structures. One such arrangement is described in the Lewis et al, U.S. Pat. No. 4,611,238. Therein is described a heat sink which mounts on the top of a semi-conductor package, with a chip being disposed within the package. Here again, the problem is that a long thermal path is required before the heat can be withdrawn from the chip's structure.
Still another problem which besets heat sinks adopted for use with TAB packages is how to support them, in an inexpensive fashion, while still retaining optimum heat dissipation characteristics. Physical interconnections to supports which are separate from the underlying circuit board make removal of the circuit board difficult. Physical interconnections to the board itself create different problems. For instance, circuit boards are often subject to flexure when they are inserted or withdrawn from mating connectors, which flexure can cause rupture of inflexible physical connections to a heat sink.
The above is not to say that prior art heat dissipation methods have been insufficient when it came to their use with low power dissipating TAB packages. So long as the chips dissipated one watt or less per chip, some of the prior art techniques were acceptable. Presently however, such TAB structures are being designed to dissipate two or more watts per chip and prior art heat dissipating techniques prove insufficient -- especially when attempting to cool the underlying chips by simple natural convective air flow -- as contrasted to forced air flow or refrigeration.
Accordingly, it is an object of this invention to provide an improved convective heat sink for a TAB mounted chip wherein the chip's power dissipation is higher than experienced in the prior art.
It is a further object of this invention to provide a TAB mounted convective heat sink which provides a very short thermal pathway for chip cooling.
It is a still further object of this invention to provide an improved convective heat sink exhibiting a minimum mass which, even when subjected to significant accelerations and deaccelerations, avoids damage to the circuit package.
It is still another object of this invention provide an improved convective heat sink which is particularly adapted for use with circuit boards which may experience flexure.